Pavan Kendaganna Swamy

Electrical Engineer

I am actively seeking full time job opportunities in the Semiconductor industry

About

Date back to 2021, after dedicating four years to Continental AG following my undergraduate studies in Electronics Engineering, I decided to relocate to the USA, to pursue my passion for designing and developing semiconductor chips. My commitment to education has never been out of compulsion but a conscious pursuit. I maintain an open mindset, always ready to learn and collaborate, which has kept my enthusiasm for engineering, particularly in VLSI. This, in combination with my minimalist approach, has led me to cultivate my skills in coding for efficiency.I had the privilege to work for Cadence Design Systems as a Product Engineer Intern. Today, my focus is on seeking a career in the semiconductor industry.In my leisure time, I indulge in activities such as painting, participating in outdoor sports, enjoying online games, or simply relishing moments of quiet reflection.I invite you to explore my online portfolio to gain insights into my qualifications and the projects!

Experiences

  1. May '22 - Dec '22
    Product Engineer Intern
    Cadence Design Systems
    1. Predominantly worked on Design Implementation flow from Placement to SignOff
    2. Timing Optimization with 30% better at SignOff
    3. Leakage Power optimization with 15% better
    Innovus
    Cerebrus
    Genus
    Tempus
    16 nm
  2. Aug '21 - May '23
    Master's in Computer Engineering (Electrical)
    Arizona State University
    1. Concentrated on Physial Design and Digital Design course work
    2. Digital Systems Circuits, VLSI Design, Constructionist Approach to Microprocessor, Logic Design using System Verilog, Python, Computer Architecture-2
    MOSFET
    ASIC
    PD flow
    Delay
    Power
    Interconnect
    STA
  3. July '17 - July '21
    Technical Specialist ADAS
    Continental AG
    1. Worked for realizing ADAS functionalitied for driver less cars
    2. Implemented ISO 26262 standard driver level software for Radar and Camera
    3. Interacted with Customer regularly in spec discussion, development, and debugging
    Davinci
    CanOe
    Leadership
    Embedded

View Full Resume

Projects

  1. Spring 2022
    2-bit Full Adder 7nm PDK
    1. Developed Verilog code for the design and synthesized netlist using Design Compiler
    2. Performed APR using Innovus and imported GDS from Innovus into cadence virtuoso layout
    3. Performed simulation using the Hspice simulator
    Innvous
    DC Compiler
    Virtuoso
    DRC
    LVS
  2. Spring 2022
    AOI22 7nm PDK
    1. Designed AOI21 schematics and layout using Cadence Virtuoso
    2. Devised test bench to observe delay and functionality by HSPICE simulation
    3. Performed LVS, DRC, and Pex extraction
    4. Compared the delay metrics of pre and post-layout simulation to understand the impact of RC delay
    5. Placed the cells in a 3x3 matrix and cleared DRC to realize the importance of compact layout design
    Virtuoso
    HSpice
    Layout
    Pex
  3. Spring 2022
    16x16 RF
    1. Designed the schematic and layout of a 16x1 Column of the RF and of 4x16 Decoder
    2. Integrated 16x1 Column Group with 4x16 Decoder to obtain 16x16 RF
    3. Verified RF functionality with test scripts.
    Virtuoso
    Hspice
  4. Fall 2021
    CMOS Digital Circuits
    1. Simulated the various basic circuits and thoroughly analyzed their delay, rise, and fall times under various constraints.
    2. Designed a 4-bit adder with 32nm technology achieving an area of 33.26 μm², a delay of 62.1pS
    3. Implemented layout of digital circuits, designing a test bench and simulation using Hspice
    Virtuoso
    HSpice
  5. Professional Development
    1. Various online resources and Udemy courses that focused on understanding critical subjects like RTL to GDSII in Physical Design and the associated issues, as well as Static Timing Analysis
    2. Scripting topics, including regular expressions (Regex) and TCL, work is documented at GitHub